Compute
Signed INT8 dot products, then tiled matrix operations.
India AI Inference Chip v1.0 is an open-source beginning for a sovereign AI stack — built in India, built with the world.

The first chip is intentionally narrow: a verifiable INT8 engine that can travel from simulation to FPGA to silicon.
Read the full blueprintSigned INT8 dot products, then tiled matrix operations.
RISC-V host, command queue, status and interrupts.
DMA and scratchpad contracts built for reproducible workloads.
FPGA evidence first, then a small open ASIC submission.
The next decade of AI will not be defined only by the biggest models in the biggest clouds. It will be defined by intelligence running everywhere — in hospitals, factories, farms, classrooms, transport, defence and homes.
Inference is the part of AI that meets the world. It turns a trained model into an action, a decision, a safer road, a more useful machine. If India does not own enough of that layer, it will depend on other countries for the intelligence inside its own infrastructure.
IAIC begins with a simple conviction: every country should be able to build a sovereign AI stack. India can contribute the silicon, the software and the open community that make that future possible.
Every camera, robot, vehicle, device and service will need to run intelligence continuously, close to the world it is observing.
A resilient AI economy needs more than models. It needs the silicon, software, tools and know-how to run them on its own terms.
We are publishing the design so universities, startups, companies and independent engineers can build in parallel and improve it in public.

The same inference layer that powers language and vision models will sit inside the machines that move through the physical world.
World models, robotics, autonomous systems, industrial inspection, medical devices, agricultural intelligence and edge vision all need fast, efficient and dependable inference — often where the cloud is too slow, too expensive or simply unavailable.
IAIC v1.0 starts narrow on purpose: an open, verifiable INT8 inference core that can move from simulation to FPGA to silicon. Then the community expands the stack around it.
Read the technical roadmapPortable, reviewable SystemVerilog at the foundation.
An open control plane for firmware, drivers and tools.
INT8-first compute for efficient edge intelligence.
A path from perception to action in the real world.
The target is a first small test chip submission by 23 July 2027. Every gate has an artifact, an owner and a review.
Open the execution roadmapAug–Sep 2026
Sep–Oct 2026
Oct–Nov 2026
Jan–Feb 2027
Mar–Jun 2027
Jul 2027
Open source is how we move fast. Hardware engineers, verification specialists, RISC-V developers, compiler builders, AI researchers, FPGA makers, educators and storytellers can all contribute from day one.
You can join from Bengaluru, Hyderabad, Delhi, anywhere in India or anywhere in the world. Start with a test, a document, a benchmark, a design review or a new idea. The project is an open-source initiative of RDP, built in public with contributors worldwide.